AD9512BCPZ

AD9512 provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part. There are five independent clock outputs. Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing adjustment. One of the LVDS/CMOS outputs features a programmable delay element with a range of up to 10ns of delay. Application includes low jitter, low phase noise clock distribution, clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs, high performance wireless transceivers, high performance instrumentation, broadband infrastructure.

• Two 1.6GHz, differential clock inputs
• 5 programmable dividers, 1 to 32, all integers
• Phase select for output-to-output coarse delay adjust
• 3 independent 1.2GHz LVPECL outputs, additive output jitter 225fs rms
• 2 independent 800MHz/250MHz LVDS/CMOS clock outputs, serial control port
• Input frequency is 1.6GHz (max, VS = 3.3V ± 5%, TA = 25°C)
• Output frequency is 800MHz (max, VS = 3.3V ± 5%, TA = 25°C)
• Output rise time is 681ps (typ, 20% to 80%, CLOAD = 3pF)
• Output fall time is 646ps (typ, 80% to 20%, CLOAD = 3pF)
• 48 lead LFCSP package, operating temperature range from -40°C to +85°C

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