ADCLK854BCPZ-REEL7

ADCLK854 is a 1.2GHz/250MHz LVDS/CMOS fan-out buffer optimized for low jitter and low power operation. Possible configurations range from 12LVDS to 24CMOS outputs, including combinations of LVDS and CMOS outputs. Three control lines are used to determine whether fixed blocks of outputs (three banks of four) are LVDS or CMOS outputs. The ADCLK854 offers two selectable inputs and a sleep mode feature. The IN-SEL pin state determines which input is fanned out to all the outputs. The SLEEP pin enables a sleep mode to power down the device. The inputs accept various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS. Typical applications include low jitter clock distribution, clock and data signal restoration, level translation, wireless communications, wired communications, medical and industrial imaging, ATE and high performance instrumentation.

• 2 selectable differential inputs and selectable LVDS/CMOS outputs
• Up to 12LVDS (1.2GHz) or 24CMOS (250MHz) outputs
• <lt/>12mW per channel (100MHz operation)
• 54fs rms integrated jitter (12KHz to 20MHz) and 150fs rms broadband random jitter
• 2.0ns typ propagation delay (LVDS) and 135ps typ output rise/fall (LVDS)
• 50ps LVDS outputs in the same bank output skew (LVDS)
• Pin programmable control and feature sleep mode
• 1.8V power supply
• 48 lead LFCSP-EP package
• Operating temperature range from -40°C to 85°C

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