LFMXO5-100T-EVN

LFMXO5-100T-EVN is a MachXO5T-NX development board. The MachXO5T-NX Development board features the LFMXO5-100T device in a 400-ball caBGA package. This device offers a variety of features and programmability that enhances Secure Control PLD functionality with Multiple Boot capabilities. Its cryptographic engine supports user-mode security features. Along with the cryptographic engine, numerous system functions are included such as four PLLs and 3,744 kbits of embedded RAM plus hardened implementations of I2C and SPI, LFMXO5-100T FPGAs feature one hard PCIe link layer IP block which supports PCIe Gen1, Gen2 with 1 or 2 x1 configuration, with flexible, high performance I/O support numerous single-ended and differential standards including LPDDR4 controller and SLVS.

• Two Gbe PHY RJ45 connectors, with SGMII PHY support
• Supports LPDDR4 upto 1066Mbps, x16 bits
• Supports PCIe Gen2 x1 edge connector
• Versa headers bridge with Lattice ASC demo board to support L-ASC10
• GPIO interface with PMOD, Arduino and Raspberry Pi boards

목차

MachXO5T-NX development board, 12V AC/DC adapter and international plug adapters, USB cable for programming via PC (USB-A to Mini-B), Quick start guide, Lattice Radiant software download information.