제품 정보
제품 개요
The SN74AUC1G74DCUR is a single positive-edge-triggered D-type Flip-flop with clear and preset. A low level at the preset (PRE\) or clear (CLR\) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, the CLR\ input overrides the PRE\ input when they are both low. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
- Ioff Supports partial-power-down mode operation
- Latch-up performance exceeds 100mA per JESD 78, Class II
- Sub-1-V Operable
- Maximum tpd of 1.5ns at 1.8V
- 10µA Maximum low power consumption
- ±8mA Output drive at 1.8V
- Green product and no Sb/Br
애플리케이션
Industrial
기술 사양
74AUC1G74
1.8ns
9mA
US8
Positive Edge
800mV
74AUC
-40°C
-
MSL 1 - Unlimited
D
275MHz
US8
8Pins
Complementary
2.7V
741G74
85°C
-
No SVHC (27-Jun-2018)
법률 및 환경
최종후의 중요 제조 공정이 이루어진 국가원산지:Thailand
최종후의 중요 제조 공정이 이루어진 국가
RoHS
RoHS
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