AD9628BCPZ-105

AD9628 is a monolithic, dual-channel, 12bit, 105MSPS ADC. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the SPI. A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. Typical applications include communications, diversity radio systems, multimode digital receivers (3G) (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA), I/Q demodulation systems, smart antenna systems, broadband data applications, battery-powered instruments, hand-held scope meters, portable medical imaging, ultrasound and radar/LIDAR.

• 1.8V analogue supply operation and 1.8V CMOS or LVDS outputs
• SNR = 71.3dBFS at 70MHz and SFDR = 90dBc at 70MHz
• 108mW typ standby power
• Differential analogue input with 650MHz bandwidth and IF sampling frequencies to 200MHz
• On-chip voltage reference and sample-and-hold circuit and 2V p-p differential analogue input
• Offset binary, Gray code, or twos complement data format and optional clock duty cycle stabilizer
• Integer 1-to-8 input clock divider and data output multiplex option
• Built-in selectable digital test pattern generation and energy-saving power-down modes
• Data clock out with programmable clock and data alignment
• 64 lead LFCSP-VQ-EP package, operating temperature range from -40°C to 85°C

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ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party