MT41K256M8DA-107:K

• DDR3L SDRAM
• 256 Meg (32) x 8 x 8 banks configuration, tCK = 1.071ns, CL = 13 speed grade
• 8K refresh count, 32KA[14:0] row address, 8BA[2:0] bank address, 1KA[9:0] column address
• VDD = VDDQ = 1.35V (1.283 to 1.45V)
• Backward-compatible to VDD = VDDQ = 1.5V ±0.075V
• Differential bidirectional data strobe, 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#), 8 internal banks
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Programmable CAS (READ) latency, programmable posted CAS additive latency
• 78-ball FBGA package, commercial temperature range from 0 to +95°C

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Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.