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수량 | 가격 |
---|---|
1+ | ₩10,783 |
10+ | ₩10,020 |
25+ | ₩9,714 |
50+ | ₩9,483 |
100+ | ₩9,253 |
250+ | ₩8,952 |
500+ | ₩8,728 |
제품 정보
제품 개요
MT46V32M16CY-5B IT:J is a double data rate (DDR) SDRAM. The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. The DDR SDRAM provide for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
- Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
- Differential clock inputs (CK and CK#), commands entered on each positive CK edge
- DQS edge-aligned with data for READs; centre aligned with data for WRITEs
- DLL to align DQ and DQS transitions with CK, four internal banks for concurrent operation
- Auto refresh – 64ms, 8192-cycle
- Longer-lead TSOP for improved reliability (OCPL)
- 2.5V I/O (SSTL-2 compatible), concurrent auto precharge option is supported
- 32 Meg x 16 configuration, timing – cycle time: 5ns at CL = 3 (DDR400)
- 8mm x 12.5mm FBGA package
- Industrial temperature range from -40°C to 85°C
경고
Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.
기술 사양
DDR
32M x 16bit
FBGA
2.6V
-40°C
-
512Mbit
200MHz
60Pins
Surface Mount
85°C
No SVHC (17-Dec-2015)
기술 문서 (1)
법률 및 환경
최종후의 중요 제조 공정이 이루어진 국가원산지:Singapore
최종후의 중요 제조 공정이 이루어진 국가
RoHS
RoHS
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