74LV132D,118

74LV132D,118 is a quad 2-input NAND gate with schmitt-trigger inputs. This device inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. It complies with JEDEC standards (JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (2.7V to 3.6V), JESD36 (4.5V to 5.5V). It features ESD protection (HBM JESD22-A114F exceeds 2000V, MM JESD22-A115-A exceeds 200V).

• Wide supply voltage range from 1V to 5.5V
• CMOS low power dissipation, optimized for low voltage applications: 1V to 3.6V
• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
• Latch-up performance exceeds 100mA per JESD 78 Class II Level B
• Output ground bounce <lt/>0.8V typical at VCC = 3.3V and Tamb = 25°C
• Input leakage current is 1μA maximum at (VI=VCC or GND;VCC = 5.5V, -40°C to +85°C)
• Supply current is 20μA maximum at (VI=VCC or GND;IO = 0A;VCC = 5.5V, -40°C to +85°C)
• Input capacitance is 3.5pF typical at (-40°C to +85°C)
• Propagation delay is 65ns typical at (VCC = 1.2V, -40°C to +85°C)
• Operating temperature range from -40°C to +125°C, SO14 package

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