8305AGLFT

ICS8305 is a low skew, 1-to-4, differential/ LVCMOS to LVCMOS/LVTTL fanout buffer. The ICS8305 has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enables pin controls whether the outputs are in the active or high impedance state. Guaranteed output and part-to-part skew characteristics make the ICS8305 ideal for those applications demanding well defined performance and repeatability.

• Four LVCMOS / LVTTL outputs, 7ohm output impedance
• Selectable differential or LVCMOS / LVTTL clock inputs
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• LVCMOS-CLK supports the following input types such as LVCMOS, LVTTL
• Maximum output frequency of 350MHz
• Output skew is 35ps (maximum)
• Part-to-part skew is 700ps (maximum), additive phase jitter, RMS is 0.04ps (typical)
• Power supply modes: core/output (3.3V/3.3V, 3.3V/2.5V, 3.3V/1.8V and 3.3V/1.5V)
• 16 lead TSSOP package
• Operating temperature range from 0°C to 70°C