HD64F2633F25V

The HD64F2633F25V is a 16-bit Single-chip Microcomputer built around the H8S/2600 CPU, employing proprietary architecture and equipped with peripheral functions on-chip. The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation and can address a 16MB linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L or H8/300H Series.

• Sixteen 16-bit General registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• High-speed operation suitable for real-time control
• 69 Basic instructions
• 8/16/32-bit Move/arithmetic and logic instructions
• Unsigned/signed multiply and divide instructions
• Multiply-and accumulate instruction
• Powerful -bit-manipulation instructions
• Two CPU operating modes
• Address space divided into 8 areas
• 3-state access space can be designated for each area
• Number of program wait states can be set for each area
• Burst ROM directly connectable
• Possible to connect a maximum of 8MB of DRAM
• External bus release function
• PC break controller
• DMA Controller (DMAC)
• Data transfer controller (DTC)
• 16-bit Timer-pulse unit (TPU)
• Programmable pulse generator (PPG)
• 4-channel 8-bit Timer
• 2-channel Watchdog timer
• 14-bit PWM timer
• 5-channel Serial communication interface (SCI)
• 1-channel IrDA-equipped SCI

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